Cadence Design Systems has entered into a definitive agreement to acquire Arm’s Artisan Foundation IP business, complementing its AI and chiplet ambitions. This includes standard cell libraries, memory compilers, and GPIOs—components critical for advanced node SoCs and modular designs.

“With the addition of Arm’s Artisan IP, Cadence will enter the foundation IP market and support new growth across design services and chiplet offerings,” said Boyd Phelps, SVP and GM of the silicon solutions group at Cadence.

The acquisition strengthens Cadence’s full-stack offering of tools, IP, and services and brings in an engineering team that will strengthen chiplet enablement.

In an exclusive conversation with EE Times, Alok Jain, corporate VP of R&D at Cadence Design Systems India, explained the company’s vision for AI-driven transformation, developing AI-enabled tools, advancing the 3D IC and chiplet-based design, and bridging the gap between academia and industry. He also talked about the company’s aggressive push to promote India as an innovation hub.

Refining chip architectures

Jain explained how the industry is rapidly shifting from monolithic SoCs to multi-die, multi-node architectures. “3D ICs and chiplets are no longer theoretical; they are production-ready,” he said, citing Intel’s Meteor Lake as an example of a real-world chiplet deployment—built using multiple foundries and process nodes.

Jain spoke about the company’s integrated 3D IC platform that combines design (Virtuoso), packaging (Allegro), and thermal and electromagnetic analysis tools from across the Cadence suite. “We are partnering with foundries like TSMC and Intel Foundry to certify and enable these 3D IC designs. Our platform is engineered to handle that level of complexity.”

Highlighting the main challenges in chiplet-based design—increased complexity, partitioning, and thermal and electromagnetic interactions—Jain said that Cadence has been partnering with outsourced semiconductor assembly and test providers to develop thermal solutions and ensure manufacturability.

Optimization AI vs. agentic AI in workflow transformation

The company is not only focused on optimizing chip design architectures but also chip design workflows, with India not limited to a contributory role but very intrinsic to Cadence’s global technology strategy, according to Jain.

“India is what I call a microcosm of the entire Cadence,” he said. “We have nearly every corporate function represented here. India is actively participating in this AI evolution.”

Driven by optimization AI and agentic AI, the company’s AI roadmap features the rollout of five AI platforms, with more in development. Jain explains that optimization AI drives iterative transitions, while agentic AI enables autonomous design decisions.

“Every EDA tool is iterative by nature; AI can make each iteration smarter—faster, more productive, and more performance-oriented,” Jain said. “We are starting with Levels 1 and 2 of agentic AI, where a human is still in the loop. The ultimate goal—Level 5—is fully autonomous design, verification, and implementation.”

But Jain is clear that AI will not replace the engineer—it will augment their decision-making, refine options, and ensure outcomes are validated. “The human will guide the AI and validate the outcomes,” he assured.

As part of Cadence’s agentic AI roadmap, teams are exploring how large language models can mine vast engineering documentation and bug repositories to enable chat-like interfaces. These embedded assistants will allow engineers to interact naturally with tools to improve usability and productivity.

“The idea is to embed some form of chat into every Cadence tool, allowing users to engage in natural dialogue to understand and use the tools more effectively,” Jain said.

Training a workforce for VLSI design and enabling startups

While technology moves forward, Cadence is also working on shaping talent pipelines around AI and chiplets to strengthen industry readiness. This includes its collaboration with the India Council for Technical Education for curriculum reforms in VLSI across 120+ Indian institutions and on-the-job training programs. Through its Cadence Academic Network, over 350 institutions in India are also given hands-on access to industry-grade tools. The company recruits directly through its Talent Pipeline Program, offering fresh graduates up to two years of on-the-job training while partnering with elite institutes such as the Indian Institute of Technology, Hyderabad and Delhi campuses, and the Indian Institute of Information Technology, Delhi, for research collaboration.

“We are working with academic institutions to ensure engineers are armed for tomorrow’s design and verification challenges,” Jain said.

Apart from academic partnerships, Cadence has an active presence within the startup ecosystem, both in India and globally. It is making its tools accessible to chip design startups and incubators through government-backed initiatives such as Chips-to-Startup. “Startups benefit not just from our tools but also from our training and networking initiatives,” Jain said.

Not limiting themselves to startups, Jain spoke about collaborative relationships with Tier 1 customers: “We work very closely with customers to help them use our tools most effectively and provide in-house training programs to support complex methodology integration.”

Concluding the discussion, Jain summed it up best when asked how Cadence balances promotion versus innovation: “The answer is both. We are constantly innovating—AI, chiplets, IP—and we are actively promoting that innovation with our customers. One cannot exist without the other.”

When Cadence first established a base in India in 1987, it had a vision to support global chip development from one of the world’s most promising talent hubs. Now the company has large R&D teams in India that play a vital role in developing design and verification IPs, and the teams are now increasingly using AI and ML techniques. Jain said India plays a key role in building internal AI systems that streamline workflow efficiency—for engineers and support teams globally. From a support center to an innovation hub, he added that Cadence India is impacting some of its most advanced developments in AI, IP, and chiplet-based design.

From EETimes